Cadence Support Site:

Cal Poly is a member of the Cadence University Program since October of 2010. The software has been operable since February 2012. Hardware was expanded to improve Cadence performance in October 2012. Due to the increase in the number of students that needed to use the Cadence tools for senior/Master's projects and class projects, additional imporovements were made Summer 2014 so as to allow for the support of 100 Cadence accounts. The system was moved to RedHat during the summer of 2015 and updated to the newest Cadence tool versions. New tools were added to the suite including ADS abilities plus additional Cadence tools were added. As of Spring 2018, over 200 accounts were being supported without problem.

We use Cadence Design Systems, Inc. products in EE431 (CAD of VLSI), EE544 (Solid-state Electronics and VLSI Laboratory) as well as in senior projects, Masters projects, and faculty research. New labs for EE307/347 (Digital integrated circuits) are being devloped for winter 2018. We have taped out multiple chips through MOSIS. Cadence and Mosis' generous support has contributed greatly to Cal Poly's integrated circuit program! 

In our young program, we use and have used Cadence* products in research projects including:

  • ICs for clear circuits on contact lenses: Receiver, transmitter, wireless on-lens battery charging and display control.
  • MCML standard cell library for low noise applications
  • SRAM compiler
  • Low power clock distribution
  • Blood glucose sensing circuit
  • UWB transceiver
  • Minimal area ADC research
  • Computer compiler
  • ... among others research projects ...
Class projects include:
  • Bandgap voltage reference research
  • SerDes circuits
  • FPGA designs
  • PWM controller
  • PUC (Physically Unclonable Constant) circuitry
  • FinFET Switched Capacitor Amplifier
  • ... among other class projects ...

Responsible Faculty and Support:

The faculty member responsible for this web page, technology files and Cadence software support is Dr. Tina Smilkstein. Professors participating in evolving Cal Poly's IC design track include Dr. John Oliver. Network technician Rob Randle maintains the hardware and is in charge of keeping the Cadence labs running smoothly.

*Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA, 95134.

(Page last modified: 7/30/2018)